? 2001 fairchild semiconductor corporation ds012447 www.fairchildsemi.com march 2001 revised august 2001 74lvth16500 low voltage 18-bit universal bus transceivers with bushold and 3-state outputs 74lvth16500 low voltage 18-bit universal bus transceivers with bushold and 3-state outputs general description the lvth16500 is an 18-bit universal bus transceiver combining d-type latches and d-type flip-flops to allow data flow in transparent, latched, and clocked modes. data flow in each direction is controlled by output-enable (oeab and oeba ), latch-enable (leab and leba), and clock (clkab and clkba ) inputs. the lvth16500 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. the transceiver is designed for low voltage (3.3v) v cc applications, but with the capability to provide a ttl inter- face to a 5v environment. the lvth16500 is fabricated with an advanced bicmos technology to achieve high speed operation similar to 5v abt while maintaining low power dissipation. features input and output interface capability to systems at 5v v cc bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs live insertion/extraction permitted power up/down high impedance provides glitch-free bus loading outputs source/sink ? 32 ma/ + 64 ma functionally compatible with the 74 series 16500 esd performance: human-body model > 2000v machine model > 200v charged-device model > 1000v also packaged in plastic fine-pitch ball grid array (fbga) (preliminary) ordering code: note 1: bga package available in tape and reel only. note 2: devices also available in tape and reel. specify by appending the suffix ?x? to the ordering code. order number package number package description 74lvth16500gx (note 1) bga54a (preliminary) 54-ball fine-pitch ball grid array (fbga), jedec mo-205, 5.5mm wide [tape and reel] 74lvth16500mea (note 2) ms56a 56-lead shrink small outline package (ssop), jedec mo-118, 0.300" wide 74lvth16500mtd (note 2) mtd56 56-lead thin shrink small outline package (tssop), jedec mo-153, 6.1mm wide
www.fairchildsemi.com 2 74lvth16500 connection diagrams pin assignment for ssop and tssop pin assignment for fbga (top thru view) pin descriptions fbga pin assignments function table (note 3) h = high voltage level l = low voltage level x = immaterial z = high impedance = high-to-low clock transition note 3: a-to-b data flow is shown: b-to-a flow is similar but uses oeba , leba, and clkba . oeba is active low. note 4: output level before the indicated steady-state input conditions were established. note 5: output level before the indicated steady-state input conditions were established, provided that clkab was low before leab went low. pin names description a 1 ? a 18 data register a inputs/3-state outputs b 1 ? b 18 data register b inputs/3-state outputs clkab , clkba clock pulse inputs leab, leba latch enable inputs oeab, oeba output enable inputs 123456 a a 2 a 1 oeab gnd b 1 b 2 b a 4 a 3 leab clkab b 3 b 4 c a 6 a 5 v cc v cc b 5 b 6 d a 8 a 7 gnd gnd b 7 b 8 e a 10 a 9 gnd gnd b 9 b 10 f a 12 a 11 gnd gnd b 11 b 12 g a 14 a 13 v cc v cc b 13 b 14 h a 16 a 15 oeab clkba b 15 b 16 j a 17 a 18 leba gnd b 18 b 17 inputs output oeab leab clkab a n b n lxxx z hhx l l hhxh h hl ll hl hh hlhxb 0 (note 4) hllxb 0 (note 5)
3 www.fairchildsemi.com 74lvth16500 functional description for a-to-b data flow, the device operates in the transparent mode when leab is high. when leab is low, the a data is latched if clkab is held at a high or low logic level. if leab is low, the a bus data is stored in the latch/flip-flop on the high-to-low transition of clkab . output-enable oeab is active-high. when oeab is high, the outputs are active. when oeab is low, the out- puts are in the high-impedance state. data flow for b-to-a is similar to that of a-to-b but uses oeba , leba, and clkba . the output enables are com- plementary (oeab is active-high and oeba is active-low). logic diagram
www.fairchildsemi.com 4 74lvth16500 absolute maximum ratings (note 6) recommended operating conditions note 6: absolute maximum continuous ratings are those values beyond which damage to the device may occur. exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. functional operation under absolute maximum rated conditions is not implied. note 7: i o absolute maximum rating must be observed. symbol parameter value conditions units v cc supply voltage ? 0.5 to + 4.6 v v i dc input voltage ? 0.5 to + 7.0 v v o dc output voltage ? 0.5 to + 7.0 output in 3-state v ? 0.5 to + 7.0 output in high or low state (note 7) v i ik dc input diode current ? 50 v i < gnd ma i ok dc output diode current ? 50 v o < gnd ma i o dc output current 64 v o > v cc output at high state ma 128 v o > v cc output at low state i cc dc supply current per supply pin 64 ma i gnd dc ground current per ground pin 128 ma t stg storage temperature ? 65 to + 150 c symbol parameter min max units v cc supply voltage 2.7 3.6 v v i input voltage 0 5.5 v i oh high-level output current ? 32 ma i ol low-level output current 64 ma t a free-air operating temperature ? 40 85 c ? t/ ? v input edge rate, v in = 0.8v ? 2.0v, v cc = 3.0v 0 10 ns/v
5 www.fairchildsemi.com 74lvth16500 dc electrical characteristics note 8: an external driver must source at least the specified current to switch from low-to-high. note 9: an external driver must sink at least the specified current to switch from high-to-low. note 10: this is the increase in supply current for each input that is at the specified voltage level rather than v cc or gnd. dynamic switching characteristics (note 11) note 11: characterized in ssop package. guaranteed parameter, but not tested. note 12: max number of outputs defined as (n). n ? 1 data inputs are driven 0v to 3v. output under test held low. symbol parameter v cc t a = ? 40 c to + 85 c units conditions (v) min max v ik input clamp diode voltage 2.7 ? 1.2 v i i = ? 18 ma v ih input high voltage 2.7 ? 3.6 2.0 v v o 0.1v or v il input low voltage 2.7 ? 3.6 0.8 v o v cc ? 0.1v v oh output high voltage 2.7 ? 3.6 v cc ? 0.2 v i oh = ? 100 a 2.7 2.4 v i oh = ? 8 ma 3.0 2.0 v i oh = ? 32 ma v ol output low voltage 2.7 0.2 v i ol = 100 a 2.7 0.5 v i ol = 24 ma 3.0 0.4 v i ol = 16 ma 3.0 0.5 v i ol = 32 ma 3.0 0.55 v i ol = 64 ma i i(hold) bushold input minimum drive 3.0 75 av i = 0.8v ? 75 av i = 2.0v i i(od) bushold input over-drive 3.0 500 a(note 8) current to change state ? 500 a(note 9) i i input current 3.6 10 av i = 5.5v control pins 3.6 1 av i = 0v or v cc data pins 3.6 ? 5 av i = 0v 1 av i = v cc i off power off leakage current 0 100 a0v v i or v o 5.5v i pu/pd power up/down 3-state 0 ? 1.5v 100 a v o = 0.5v to 3.0v output current v i = gnd or v cc i ozl 3-state output leakage current 3.6 ? 5 av o = 0.0v i ozh 3-state output leakage current 3.6 5 av o = 3.6v i ozh + 3-state output leakage current 3.6 10 av cc < v o 5.5v i cch power supply current 3.6 0.19 ma outputs high i ccl power supply current 3.6 5 ma outputs low i ccz power supply current 3.6 0.19 ma outputs disabled i ccz + power supply current 3.6 0.19 ma v cc v o 5.5v, outputs disabled ? i cc increase in power supply current 3.6 0.2 ma one input at v cc ? 0.6v (note 10) other inputs at v cc or gnd symbol parameter v cc t a = 25 c units conditions (v) min typ max c l = 50 pf, r l = 500 ? v olp quiet output maximum dynamic v ol 3.3 0.8 v (note 12) v olv quiet output minimum dynamic v ol 3.3 ? 0.8 v (note 12)
www.fairchildsemi.com 6 74lvth16500 ac electrical characteristics note 13: skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of th e same device. the specification applies to any outputs switching in the same direction, either high-to-low (t oshl ) or low-to-high (t oslh ). capacitance (note 14) note 14: capacitance is measured at frequency f = 1 mhz, per mil-std-883, method 3012. symbol parameter t a = ? 40 c to + 85 c, c l = 50 pf, r l = 500 ? units v cc = 3.3 0.3v v cc = 2.7v minmaxminmax f max clkab or clkba to b or a 150 150 mhz t plh propagation delay 1.3 5.2 1.3 5.8 ns t phl data to outputs 1.3 4.7 1.3 5.3 t plh propagation delay 1.5 5.5 1.5 6.3 ns t phl leba or leab to b or a 1.5 5.1 1.5 5.7 t plh propagation delay 1.3 5.8 1.3 6.9 ns t phl clkba or clkab to b or a 1.2 5.0 1.3 5.9 t pzh output enable time 1.2 5.0 1.3 5.7 ns t pzl 1.3 5.5 1.3 6.5 t phz output disable time 1.7 6.0 1.7 6.7 ns t plz 1.6 5.8 1.7 6.3 t su setup time a before clkab 2.9 2.9 ns b before clkba 2.9 2.9 a or b before le, clk high 1.8 0.9 a or b before le, clk low 2.9 2.3 t h hold time a or b after clk 0.5 0.9 ns a or b after le 1.6 1.6 t w pulse duration le high 3.3 3.3 ns clk high or low 3.3 3.3 t oslh output to output skew (note 13) 1.0 1.0 ns t oshl 1.0 1.0 symbol parameter conditions typical units c in input capacitance v cc = 0v, v i = 0v or v cc 4pf c i/o input/output capacitance v cc = 3.0v, v o = 0v or v cc 8pf
7 www.fairchildsemi.com 74lvth16500 physical dimensions inches (millimeters) unless otherwise noted 54-ball fine-pitch ball grid array (fbga), jedec mo-205, 5.5mm wide package number bga54a preliminary
www.fairchildsemi.com 8 74lvth16500 physical dimensions inches (millimeters) unless otherwise noted (continued) 56-lead shrink small outline package (ssop), jedec mo-118, 0.300" wide package number ms56a
9 www.fairchildsemi.com 74lvth16500 low voltage 18-bit universal bus transceivers with bushold and 3-state outputs physical dimensions inches (millimeters) unless otherwise noted (continued) 56-lead thin shrink small outline package (tssop), jedec mo-153, 6.1mm wide package number mtd56 fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild ? s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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